A system design approach toward integrated cryogenic quantum control systems

In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG's), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics

MuPix & ATLASpix: Architectures and Results

High Voltage Monolithic Active Pixel Sensors (HV-MAPS) are based ona commercial High Voltage CMOS process and collect charge by driftinside a reversely biased diode. HV-MAPS represent a promising technology for future pixel tracking detectors. Two recent developments are presented. The MuPix has a continuous readout and is being developed for the Mu3e experiment whereas the ATLASPix is being developed for LHC applications with a triggered readout. Both variants have a fully monolithic design including state machines, clock circuitries and serial drivers. Several prototypes and design variants were characterised in the lab and in testbeam campaigns to measure efficiencies, noise, time resolution and radiation tolerance. Results from recent MuPix and ATLASPix prototypes are presented and prospects for future improvements are discussed.High Voltage Monolithic Active Pixel Sensors (HV-MAPS) are based on a commercial High Voltage CMOS process and collect charge by drift inside a reversely biased diode. HV-MAPS represent a promising technology for future pixel tracking detectors. Two recent developments are presented. The MuPix has a continuous readout and is being developed for the Mu3e experiment whereas the ATLASPix is being developed for LHC applications with a triggered readout. Both variants have a fully monolithic design including state machines, clock circuitries and serial drivers. Several prototypes and design variants were characterised in the lab and in testbeam campaigns to measure efficiencies, noise, time resolution and radiation tolerance. Results from recent MuPix and ATLASPix prototypes are presented and prospects for future improvements are discussed

High-Voltage CMOS Active Pixel Sensor

International audienceThe high-voltage CMOS (HVCMOS) sensors are a novel type of CMOS active pixel sensors for ionizing particles that can be implemented in CMOS processes with deep n-well option. The pixel contains one sensor electrode formed with a deep n-well implanted in a p-type substrate. CMOS pixel electronics, embedded in shallow wells, are placed inside the deep n-well. By biasing the substrate with a high negative voltage and by the use of a lowly doped substrate, a depleted region depth of at least 30 μm can be achieved. The electrons generated by a particle are collected by drift, which induces fast detectable signals. This publication presents a 4.2-cm 2 large HVCMOS pixel sensor implemented in a commercial 180-nm process on a lowly doped substrate and its characterization

An 8b 1.0-to-1.25GS/s Time-Based ADC with Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC

An 8-bit digital intensive time-based ADC implemented in 5nm CMOS is presented in this work. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the reference voltage and to allow a wide input swing of 0.75Vpp,diff. A redundancy scheme for the input polarity decision taken for 1-bit voltage domain folding is introduced against wrong decisions which eliminates comparator calibration in analog domain and allows a more efficient design. Sense amplifier latch (SAL) interpolation technique is presented which reduces the power and area consumption when phase interpolating the time-to-digital converter (TDC) signals. The ADC reaches 1GS/s sampling rate with 0.7V supply and 1.25GS/s with 0.8V supply and achieves 16.6fJ/conv-step and 20.3fJ/conv-step Walden FoM respectively. The total active area is 313μm2.ISSN:2573-960

Design of a HVCMOS pixel sensor ASIC with on-chip readout electronics for ATLAS ITk Upgrade

International audienceATLASpix is a series of monolithic High Voltage CMOS (HVCMOS) sensor chips that are engineered to meet the requirements of outer layers of ATLAS ITk pixel tracker for HL-LHC upgrade. They are large collection electrode designs on high resistive wafers to ensure high detection efficiency and radiation tolerance. The readout electronics are placed on the chip periphery. ATLASpix1_M2 prototype is fabricated in a commercial 180 nm CMOS technology and has an active area of 1.6 cm × 0.33 cm. No clock signals are propagated inside the pixel matrix reducing the crosstalk and helping to achieve an estimated power consumption of 300 mW/cm$^2$. This work presents the design of ATLASpix_M2 with emphasis on its readout electronics, together with some experimental results

A high-voltage pixel sensor for the ATLAS upgrade

High Voltage CMOS (HVCMOS) pixel sensors have been proposed for upgrade of the ATLAS experiment and for the tracking detectors at future colliders. They are implemented in commercial HVCMOS technologies, which makes the production cost effective when compared to hybrid pixel detectors. The HVCMOS detectors are monolithic, which means that the readout electronics and the sensor part are implemented on the same substrate. A high voltage is used to create a depletion region where the particle detection occurs. A large area prototype for the ATLAS experiment named ”ATLASpix” has been designed and fabricated in the AMS 180 HVCMOS process technology. ATLASpix includes different design flavors in terms of pixel size and readout logic. HVCMOS pixel sensors have been fabricated using wafers of different resistivity. Design details and measurement results are presented